EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
Design-Reuse

eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool

GUI based tool targeted to reduce verification time and maximize memory coverage Ahmedabad -- June 2, 2009 -- eInfochips, Inc., a leading IP driven ASIC/FPGA/SoC, Embedded Systems & Software design ...
Design-Reuse

Synopsys to Release a Complete, Single Vendor Interface IP for High-Performance DDR2 SDRAM Memory Subsystems

Complete Solution Will Include Memory Controller and Mixed-Signal PHY to Reduce Risk and Speed System Integration MOUNTAIN VIEW, Calif., October 30, 2006 - Synopsys, Inc. (Nasdaq:SNPS), a world leader ...
HotHardware

DDR2 Shoot-Out: Corsair vs. Kingston

With the launch of their 900 series chipsets, and LGA775 based Pentium 4 processors, Intel introduced the use of DDR2 system memory on the desktop. DDR1 system memory had been the standard for quite a ...